1. Field of the Invention
The present invention relates to powering up voltage domains of a DRAM after exiting a powerdown event, and more particularly, to a system for enabling fast powering up of voltage domains of a DRAM after exiting a powerdown event.
2. Description of the Prior Art
In conventional low power DRAM design, during a powerdown event, local voltage power domains are also powered down. When exiting the powerdown event, all parasitic and decoupling capacitances attached to these local voltage power domains need to be recharged to their full amount, which could require a significant amount of time and could place a burden on the system. For instance, if normal operations resume before complete recharging has occurred, data maybe invalid.
In a conventional DRAM circuit, power is supplied to the local voltage power domains by either an external power supply or through a voltage regulator. Referring to FIG. 1 and FIG. 2 which are circuit diagrams illustrating conventional DRAM systems. FIG. 1 is a diagram of an unregulated power domain 100 of a DRAM, wherein a capacitor C is coupled between a Local Domain Power Supply voltage VLPD and ground. The coupling or decoupling of the capacitor C is according to a signal CKE which controls the powerdown operation of the DRAM. The system 100 also comprises an inverter 150, which is for inverting the signal CKE to generate an inverted signal CKEF.
In a powerdown operation, CKE will transition to low and CKEF will transition to high. CKEF is then input to the gate of a transistor (PMOS) P which is coupled between a supply Vcc and the Local Power Domain Supply voltage VLPD. This causes the transistor P to switch off, leaving VLPD floating. VLPD will eventually reach 0 volts over time. When powerdown mode is exited (CKE transitions to high, CKEF transitions to low so transistor P is turned on), capacitor C needs to be fully charged and VLPD needs to reach full potential before the system 100 is able to properly deal with commands issued by the DRAM.
FIG. 2 is a circuit diagram of a conventional DRAM system illustrating a regulated local power domain 200 of a DRAM. The system 200 includes a regulator 225 coupled to VLPD via its output. The regulator 225 is also supplied with a reference signal REF and the powerdown signal CKE. When CKE is in the low state, the regulator 225 will not supply an output to the capacitor C so that VLPD will be floating. VLPD will eventually reach 0 volts over time. When CKE is in the high state, the regulator 225 will perform the VLPD pull-up and charging of the capacitor C.
As stated above, when exiting powerdown mode, the decoupling capacitor C must be fully charged so that VLPD can reach full potential before commands are issued; otherwise, there is the risk of invalid data being generated. The size of the decoupling capacitances used in low power domains often means that a long time is required to fully charge the decoupling and parasitic capacitors. The time needed to charge up the capacitance could be reduced if the size of the decoupling capacitance were reduced. This, however, would result in large voltage drops during normal operations of the DRAM, and also increase the amount of noise in the system.